Silicon-on-insulator (SOI) technology has become an increasingly important technique utilized in the fabrication and production of semiconductor devices. SOI technology deals with the formation of transistors in a relatively thin monocrystalline semiconductor layer, which overlays an insulating layer. In other words, the active devices are formed in a thin semiconductor on an insulator layer rather than in the bulk semiconductor of the device. SOI technology makes possible certain performance advantages, such-as the reduction of parasitic elements present in integrated circuits formed in bulk semiconductors, useful in high performance and high-density integrated circuits. SOI technology further allows for the mapping of standard advanced technologies into a SOI technology without significant modifications, and exhibits its advantages for higher speed, lower power consumption and better radiation immunity due to the enhanced isolation of buried oxide layers.
On a typical SOI transistor, however, the body is generally isolated from the silicon substrate and usually kept floating, and this may result in serious problems for current-sensitive circuit applications. The body retains charges and some of the electrical properties from the last time the transistor was used, interfering with subsequent use of the device. A variety of solutions have been proposed to address the problems associated with the SOI semiconductor device. For example, the use of a body contact in the SOI device addresses this problem, and also allows the threshold voltage to be changed so that standby power can be reduced for low-power applications. The body contact in the SOI device has conventionally been made by the use of a T-shaped or a H-shaped polysilicon structure on an active area, thereby creating three distinct regions including a source region, a drain region, and a body contact region.
FIG. 1A is a top view illustrating a conventional T-shaped polysilicon structure with a body contact. FIG. 1B is a cross-sectional view along line 1B-1B in FIG. 1A. FIG. 1C is a cross-sectional view along line 1C-1C in FIG. 1A. An SOI substrate 10, typically including a silicon base layer, a buried oxide layer and a semiconductor silicon layer (e.g., a P type layer), is provided with an active area 12 defined by a shallow trench isolation (STI) structure 14 formed in the semiconductor silicon layer over the buried oxide layer. A T-shaped polysilicon layer 16 is formed on the active area 12, thus creating three distinct regions including a source region 17, a drain region 18, and a body contact region 20 in the semiconductor silicon layer For an example of NMOS device, the source region 17 and the drain region 18 are N+-type regions, and the body contact region 20 is a P+-type region. FIG. 2A is a top view illustrating a conventional H-shaped polysilicon structure with body contacts. FIG. 2B is a cross-sectional view along line 2B-2B in FIG. 2A. FIG. 2C is a cross-sectional view along line 2C-2C in FIG. 2A. Explanation of the same or similar portions to the description in FIGS. 1A-1C is omitted herein. By comparison, the T-shaped polysilicon layer 16 is replaced with a H-shaped polysilicon layer 16″, thus creating four distinct regions. The conventional approaches increase parasitic diode due to increased P+/P−/N+ junction areas, thus improving the current sink capacity in the body contact region. The T-shaped or H-shaped polysilicon layer, however, including a polysilicon gate portion and a polysilicon dummy portion, induces high gate capacitance, usually causing poor performance.
Therefore, there exists a need for a SOI MOSFET device that allows a reduction of polysilicon loading on the active area to overcome problems arising from high gate capacitance.